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8700f?seepr?6/12 features ? low-voltage operation ? v cc = 1.7v to 5.5v ? internally organized as 128 x 8 (1k) or 256 x 8 (2k) ? i 2 c compatible (2-wire) serial interface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 400khz (1.7v) and 1mhz (2.5v, 2.7v, 5.0v) compatibility ? write protect pin for hardware data protection ? 8-byte page write mode ? partial page writes allowed ? self-timed write cycle (5ms max) ? high-reliability ? endurance: 1,000,000 write cycles ? data retention: 100 years ? green package options (pb/halide-free/rohs-compliant) ? 8-lead pdip, 8-lead jedec soic, 8-lead tssop, 8-pad udfn, 5-lead sot23, and 8-ball vfbga ? die sale options: wafer form and tape and reel available description the atmel ? at24c01c/02c provides 1024/2048-bits of serial electrically erasable and programmable read-only memory (eeprom) organized as 128/256 words of eight bits each. both devices include a cascading feature that allows up to eight devices to share a common 2-wire bus. these devices are optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. the at24c01c/02c are available in space saving 8-lead pdip, 8-lead jedec soic, 8-lead tssop, 8-lead udfn , 5-lead sot23, and 8-ball vfbga packages. in addition, the entire family operates from 1.7v to 5.5v v cc . atmel at24c01c and AT24C02C i 2 c-compatible (2-wire) serial eeprom 1-kbit (128 x 8), 2-kbit (256 x 8) datasheet
2 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 1. pin configurations and pinouts note: 1. for use of 5-lead sot23, the software a2, a1, and a0 bits in the device address word must be set to zero to properly communicate. 2. absolute maximum ratings pin name function a 0 - a 2 address inputs sda serial data scl serial clock input wp write protect gnd ground v cc power supply 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc wp scl sda 8-lead soic 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc wp scl sda 8-lead pdip 1 2 3 5 4 scl gnd sda wp v cc 5-lead sot23 1 2 3 4 8 7 6 5 v cc wp scl sda a 0 a 1 a 2 gnd 8-lead udfn bottom view v cc wp scl sda a 0 a 1 a 2 gnd 1 2 3 4 8 7 6 5 8-ball vfbga bottom view 1 2 3 4 8 7 6 5 a 0 a 1 a 2 gnd v cc wp scl sda 8-lead tssop (1) operating temperature ........................?55 ? c to +125 ? c storage temperature ...........................?65 ? c to +150 ? c voltage on any pin with respect to ground .............................?1.0v to +7.0v maximum operating voltage ................................. 6.25v dc output current................................................ 5.0ma *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 3. block diagram 4. pin description serial clock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. serial data (sda): the sda pin is bidirectional for serial data transfer. this pin is open drain driven and may be wire-ored with any number of other open drain or open collector devices. device/page addresses (a 2 , a 1 , a 0 ): the a 2 , a 1 , and a 0 pins are device address inputs that are hard wired for the at24c01c/02c. as many as eight 1-kbit or 2-kbit devices may be addressed on a single bus system. see section 7. ?device addressing? on page 9 for more details. write protect (wp): the at24c01c/02c have a write protect pin that provides hardware data protection. the write protect pin allows normal read/write operations when connected to ground (gnd). when the write protect pin is connected to v cc , the write protection feature is enabled and operates as shown below in table 4-1 . table 4-1. write protect start stop logic v cc gnd wp scl sda a 2 a 1 a 0 serial control logic en h.v. pump/timing eeprom data recovery serial mux x dec d out /ack logic comp load inc data word addr/counter y dec r/w d out d in load device address comparator wp pin status part of the array protected atmel at24c01c and AT24C02C at v cc full (2k) array at gnd normal read/write operations
4 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 5. memory organization atmel at24c01c, 1k serial eeprom: internally organized with 16 pages of eight bytes each, the 1k requires a 7-bit data word address for random word addressing. atmel AT24C02C, 2k serial eeprom: internally organized with 32 pages of eight bytes each, the 2k requires an 8-bit data word address for random word addressing. table 5-1. pin capacitance (1) note: 1. this parameter is characterized and is not 100% tested. table 5-2. dc characteristics note: 1. v il min and v ih max are reference only and are not tested. applicable over recommended operating range from t a = 25 ? c, f = 1.0mhz, v cc = 1.7v to 5.5v symbol test condition max units conditions c i/o input/output capacitance (sda) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v applicable over recommended operating range from: t ai = ?40c to +85c, v cc = 1.7v to 5.5v (unless otherwise noted) symbol parameter test condition min typ max units v cc1 supply voltage 1.7 5.5 v v cc2 supply voltage 2.5 5.5 v v cc3 supply voltage 4.5 5.5 v i cc1 supply current v cc = 5.0v read at 400khz 0.4 1.0 ma i cc2 supply current v cc = 5.0v write at 400khz 2.0 3.0 ma i sb1 standby current v cc = 1.7v v in = v cc or v ss 1.0 a i sb2 standby current v cc = 2.5v v in = v cc or v ss 2.0 a i sb3 standby current v cc = 5.5v v in = v cc or v ss 6.0 a i li input leakage current v in = v cc or v ss 0.10 3.0 a i lo output leakage current v out = v cc or v ss 0.05 3.0 a v il input low level (1) ?0.6 v cc x0.3 v v ih input high level (1) v cc x0.7 v cc +0.5 v v ol1 output low level v cc = 1.7v i ol = 0.15ma 0.2 v v ol2 output low level v cc = 3.0v i ol = 2.1ma 0.4 v
5 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 table 5-3. ac characteristics note: 1. this parameter is ensured by characterization only. 2. ac measurement conditions: ? r l (connects to v cc ): 1.3 k ? (2.5v, 5v), 10 k ? (1.7v) ? input pulse voltages: 0.3 v cc to 0.7 v cc ? input rise and fall times: ? 50ns ? input and output timing reference voltages: 0.5 v cc applicable over recommended operating range from t ai = ? 40 ? c to +85 ? c, v cc = 1.7v to 5.5v, cl = 1ttl gate and 100pf (unless otherwise noted). test conditions are listed in note 2 . symbol parameter 1.7v 2.5v,5.0v units min max min max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.2 0.4 s t high clock pulse width high 0.6 0.4 s t i noise suppression time 100 50 ns t aa clock low to data out valid 0.1 0.9 0.05 0.55 s t buf time the bus must be free before a new transmission can start. 1.2 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start setup time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time (1) 0.3 0.3 s t f inputs fall time (1) 300 100 ns t su.sto stop setup time 0.6 .25 s t dh data out hold time 50 50 ns t wr write cycle time 5 5 ms endurance (1) 3.3v, +25 ? c, page mode 1,000,000 write cycles
6 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 6. device operation clock and data transitions: the sda pin is normally pulled high with an external device. data on the sda pin may change only during scl low time periods (see figure 6-4 on page 8 ). data changes during scl high periods will indicate a start or stop condition as defined below. start condition: a high-to-low transition of sda with scl high is a start condition which must precede any other command (see figure 6-5 on page 8 ). stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode (see figure 6-5 on page 8 ). acknowledge: all addresses and data words are serially transmitted to and from the eeprom in 8-bit words. the eeprom sends a zero to acknowledge that it has received each word. this happens during the ninth clock cycle. standby mode: the at24c01c/02c features a low power standby mode which is enabled: ? upon power-up. ? after the receipt of the stop bit and the completion of any internal operations. 2-wire software reset: after an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: 1. create a start bit condition. 2. clock nine cycles. 3. create another start bit followed by stop bit condition as shown in figure 6-1 . the device is ready for the next communication after above steps have been completed. figure 6-1. software reset scl 9 start bit start bit stop bit 8 3 2 1 sda dummy clock cycles
7 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 figure 6-2. bus timing scl: serial clock, sda: serial data i/o figure 6-3. write cycle timing scl: serial clock, sda: serial data i/o notes: 1. the write cycle time t wr is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. scl sda in sda out t f t high t low t low t r t aa t dh t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta t wr (1) stop condition start condition word n ack 8 th bit scl sda
8 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 figure 6-4. data validity figure 6-5. start and stop definition figure 6-6. output acknowledge sda scl data stable data stable data change sda scl start stop scl data in data out start acknowledge 9 8 1
9 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 7. device addressing the 1-kbit and 2-kbit eeprom device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation. the device address word consists of a mandatory ?1010? (0xa) sequence for the first four most significant bits as shown in figure 7-1 . this is common to all serial eeprom devices. the next three bits are the a2, a1, and a0 device address bits for the 1k and 2k eeprom. these three bits must compare to their corresponding hard-wired input pins a 2 , a 1 , and a 0 in order for the part to acknowledge. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a valid compare of the device address with hard-wired input pins a 2 , a 1 , and a 0 , the eeprom will output a zero. if a compare is not successfully made, the chip will return to a standby state. figure 7-1. device address 8. write operations byte write: a byte write operation requires an 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. at this time, the eeprom enters an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete (see figure 9-1 on page 10 ). page write: the 1-kbit and 2-kbit eeprom are capable of an 8-byte page write. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, after the eeprom acknowledges receipt of the first data word, the microcontroller can transmit up to seven data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 9-2 on page 10 ). the data word address lower three bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eight data words are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally timed write cycle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero allowing the read or write sequence to continue. data security: the at24c01c/02c has a hardware data protection scheme that allows the user to write protect the entire memory when the wp pin is at v cc . 1 0 1 0 a2 a1 a0 r/w 1k or 2k msb lsb
10 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 9. read operations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: ? current address read ? random address read ? sequential read. current address read: the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as the chip power is maintained. the address roll-over during read is from the last byte of the last memory page to the first byte of the first page. the address roll-over during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to one is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an zero but does generate a following stop condition (see figure 9-3 on page 11 ). random read: a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the eeprom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out the data word. the microcontroller does not respond with a zero but does generate a following stop condition (see figure 9-4 on page 11 ). sequential read: sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll-over and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see figure 9-5 on page 11 ). figure 9-1. byte write figure 9-2. page write sda line s t a r t w r i t e s t o p device address word address data m s b a c k a c k a c k r / w sda line s t a r t w r i t e s t o p device address word address (n) data (n) data (n + 1) data (n + x) m s b a c k a c k a c k a c k a c k r / w
11 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 figure 9-3. current address read figure 9-4. random read figure 9-5. sequential read sda line s t a r t r e a d s t o p device address data m s b a c k n o a c k r / w sda line s t a r t s t a r t r e a d w r i t e s t o p device address device address word address (n) data (n) m s b a c k a c k a c k n o a c k r / w dummy write sda line r e a d s t o p device address data (n) data (n + 1) data (n + 2) data (n + x) m s b a c k a c k a c k a c k n o a c k r / w
12 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 10. ordering code detail atmel designator product family device density device revision shipping carrier option operating voltage 01 = 1-kbit 02 = 2-kbit b or blank = bulk (tubes) t = tape and reel m = 1.7v to 5.5v package device grade or wafer/die thickness u = green, matte sn lead finish, industrial temperature range (-40?c to +85?c) h = green, nipdau lead finish, industrial temperature range (-40?c to +85?c) 11 = 11mil wafer thickness package option p = pdip ss = jedec soic x = tssop ma = udfn st = sot23 c = vfbga wwu = wafer unsawn at24c01c-sshm-b
13 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 11. part markings drawing no. rev. title catalog number truncation at24c01c truncation code ###: 01c AT24C02C truncation code ###: 02c aaaaaaaa ###m @ atmluyww 8-lead pdip aaaaaaaa ###m @ atmlhyww 8-lead soic 8-lead tssop aaaaaaa ###m @ athyww ###u @ymxx 2.35 x 3.73 mm body 8-ball vfbga 8-lead udfn ### hm@ yxx 2.0 x 3.0 mm body 5-lead sot-23 ###mu ymxx bottom mark top mark note 2: package drawings are not to scale note 1: designates pin 1 package mark contact: dl-cso-assy_eng@atmel.com 24c01-02csm a 5/4/12 24c01-02csm, at24c01c and AT24C02C package marking information date codes voltages y = year m = month ww = work week of assembly m: 1.7v min 2: 2012 6: 2016 a: january 02: week 2 3: 2013 7: 2017 b: february 04: week 4 4: 2014 8: 2018 ... ... 5: 2015 9: 2019 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number u: industrial/matte tin h: industrial/nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel at24c01c and AT24C02C: package marking information
14 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 12. ordering codes 12.1 atmel at24c01c ordering information notes: 1. b = bulk (tubes) 2. t = tape and reel ? soic = 4k per reel ? tssop, udfn, sot23, and vfbga = 5k per reel 3. for wafer sales, please contact atmel sales. ordering code package voltage operation range at24c01c-pum (bulk form only) 8p3 1.7v to 5.5v lead-free/halogen-free/ industrial temperature (?40 ? c to 85 ? c) at24c01c-sshm-b (1) (nipdau lead finish) 8s1 at24c01c-sshm-t (2) (nipdau lead finish) 8s1 at24c01c-xhm-b (1) (nipdau lead finish) 8x at24c01c-xhm-t (2) (nipdau lead finish) 8x at24c01c-mahm-t (2) (nipdau lead finish) 8ma2 at24c01c-stum-t (2) 5ts1 at24c01c-cum-t (2) 8u3-1 at24c01c-wwu11m (3) wafer sale industrial temperature (?40 ? c to 85 ? c) package type 8p3 8-lead, 0.300" wide, plastic dual inline (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8x 8-lead, 4.4mm body, plastic thin shrink small outline (tssop) 8ma2 8-lead, 2.00mm x 3.00mm body, 0.50mm pitch, ultra thin dual flat no lead (udfn) 5ts1 5-lead, 2.90mm x 1.60mm body, plastic thin shrink small outline (sot23) 8u3-1 8-ball, die ball grid array (vfbga)
15 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 12.2 atmel AT24C02C ordering information notes: 1. b = bulk (tubes) 2. t = tape and reel ? soic = 4k per reel ? tssop, udfn, sot23, and vfbga = 5k per reel 3. for wafer sales, please contact atmel sales. ordering code package voltage operation range AT24C02C-pum (bulk form only) 8p3 1.7v to 5.5v lead-free/halogen-free/ industrial temperature (?40 ? c to 85 ? c) AT24C02C-sshm-b (1) (nipdau lead finish) 8s1 AT24C02C-sshm-t (2) (nipdau lead finish) 8s1 AT24C02C-xhm-b (1) (nipdau lead finish) 8x AT24C02C-xhm-t (2) (nipdau lead finish) 8x AT24C02C-mahm-t (2) (nipdau lead finish) 8ma2 AT24C02C-stum-t (2) 5ts1 AT24C02C-cum-t (2) 8u3-1 AT24C02C-wwu11m (3) wafer sale industrial temperature (?40 ? c to 85 ? c) package type 8p3 8-lead, 0.300" wide, plastic dual inline (pdip) 8s1 8-lead, 0.150" wide, plastic gull wing small outline (jedec soic) 8x 8-lead, 4.4mm body, plastic thin shrink small outline (tssop) 8ma2 8-lead, 2.00mm x 3.00mm body, 0.50mm pitch, ultra thin dual flat no lead (udfn) 5ts1 5-lead, 2.90mm x 1.60mm body, plastic thin shrink small outline (sot23) 8u3-1 8-ball, die ball grid array (vfbga)
16 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13. packaging information 13.1 8p3 ? 8-lead pdip drawing no. rev. title gpc notes: 1. this drawing is for general information only; refer to jedec drawing ms-001, variation ba for additional information. 2. dimensions a and l are measured with the package seated in jedec seating plane gauge gs-3. 3. d, d1 and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0.25 mm). common dimensions (unit of measure = inches) symbol min nom max note d d1 e e1 e l b2 b a2 a 1 n ea c b3 4 plcs a 0.210 2 a2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 d 0.355 0.365 0.400 3 d1 0.005 3 e 0.300 0.310 0.325 4 e1 0.240 0.250 0.280 3 e 0.100 bsc ea 0.300 bsc 4 l 0.115 0.130 0.150 2 top view side view end view package drawing contact: packagedrawings@atmel.com 8p3 d 06/21/11 8p3, 8-lead, 0.300?wide body, plastic dual in-line package (pdip) ptc
17 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13.2 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ?1.75 b 0.31 ?0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ?6.20 e 1.27 bsc l 0.40 ?1.27 0? ? 8 e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150?wide body), plastic gull wing small outline (jedec soic) swb
18 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13.3 8x ? 8-lead tssop drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side view end view top view a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information only. refer to jedec drawing mo-153, variation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. package drawing contact: packagedrawings@atmel.com 8x d 6/22/11 8x, 8-lead 4.4mm body, plastic thin shrink small outline package (tssop) tnr c a1
19 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13.4 8ma2 ? 8-pad udfn title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8ma2 ynz b 8ma2, 8-pad, 2 x 3 x 0.6 mm body, thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max note d 2.00 bsc e 3.00 bsc d2 1.40 1.50 1.60 e2 1.20 1.30 1.40 a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 0.55 c 0.152 ref l 0.30 0.35 0.40 e 0.50 bsc b 0.18 0.25 0.30 3 k 0.20 ? 7/15/11 d2 e2 e e (6x) l (8x) b (8x) pin#1 id a a1 a2 pin 1 id d c k 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5
20 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13.5 5ts1 ? 5-lead sot23 drawing no. rev. title gpc package drawing contact: packagedrawings@atmel.com 5ts1 d 5/31/12 5ts1, 5-lead 1.60mm body, plastic thin shrink small outline package (shrink sot) tsz common dimensions (unit of measure = mm) symbol min nom max note a - - 1.00 a1 0.00 - 0.10 a2 0.70 0.90 1.00 c 0.08 - 0.20 3 d 2.90 bsc 1,2 e 2.80 bsc 1,2 e1 1.60 bsc 1,2 l1 0.60 ref e 0.95 bsc e1 1.90 bsc b 0.30 - 0.50 3,4 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 mm per side. 2. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. these dimensions apply to the flat section of the lead between 0.08 mm and 0.15 mm from the lead tip. 4. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the foot. minimum space between protrusion and an adjacent lead shall not be less than 0.07 mm. this drawing is for general information only. refer to jedec drawing mo-193, variation ab for additional information. 5 4 2 l1 l c end view c a a2 a1 b e plane seating d side view e e1 e1 3 1 top view
21 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 13.6 8u3-1 ? 8-ball vfbga drawing no. rev. title gpc package drawing contact: packagedrawings@atmel.com 8u3-1 e 3/27/12 8u3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, vfbga package gxu common dimensions (unit of measure - mm) symbol min nom max note a 0.73 0.79 0.85 a1 0.09 0.14 0.19 a2 0.40 0.45 0.50 b 0.20 0.25 0.30 2 d 1.50 bsc e 2.0 bsc e 0.50 bsc e1 0.25 ref d 1.00 bsc d1 0.25 ref 1. this drawing is for general information only. 2. dimension ? is measured at maximum solder ball diameter. 3. solder ball composition shall be 95.5sn-4.0ag-.5cu. notes: a2 side view a pin 1 ball pad corner top view e d a1 b 8 solder balls bottom view (d1) d 4 3 2 (e1) 6 e 5 7 pin 1 ball pad corner 1 8 2.
22 atmel at24c01c/02c [datasheet] 8700f?seepr?6/12 14. revision history doc. rev. date comments 8700f 06/2012 correct ordering codes: - at24c01c-wwu11, die sale to at24c01c-wwu11m, wafer sale. - AT24C02C-wwu11, die sale to AT24C02C-wwu11m, wafer sale. remove wdt from ordering code detail. update atmel logos and disclaimer page. 8700e 05/2012 update datasheet template. add at24c01c to document. electrical performance improvements: - reduce all isb from legacy values - increase 1mhz frequency range to include 2.5v operation. update package drawings to latest versions (where applicable) and selected waveforms. 8700d 08/2010 change AT24C02C-xhm part marking from c02cm@ to 02cm @. 8700c 07/2010 ordering information: - change atmel AT24C02C-tsum-t to atmel AT24C02C-stum-t. - change atmel AT24C02Cy6-mahm-t to atmel AT24C02C-mahm-t. - change atmel AT24C02Cu3-cum-t to atmel AT24C02C-cum-t. catalog numbering scheme, change ts = sot23 to st = sot23. part marking sot23: - change 2cmwu to 2cmbu. - change w = write protection feature to b = write protection. part marking pdip and soic: added @ = country of assembly. part marking tssop: replaced and removed bottom mark. part marking udfn: added hm@. remove preliminary status. change t i max 40 to 50 in table ac characteristics. 8700b 02/2010 correct catalog numbering scheme and ordering information. 8700a 12/2009 initial document release.
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